A ferroelectric nonvolatile random access memory uses a ferroelectric capacitor as a storage element of each memory cell. Each memory cell stores a logic state based on the electrical polarization of the ferroelectric capacitor. The ferroelectric capacitor has a dielectric between its electrodes that comprises a ferroelectric material such as lead zirconate titanate (PZT). When a voltage is applied to the plates of the capacitor, the ferroelectric material is polarized in the direction of the electric field. The switching threshold for changing the polarization state of the ferroelectric capacitor is defined as the coercive voltage. The ferroelectric capacitor exhibits hysteresis, and the flow of current to the capacitor depends on its polarization state. If the voltage applied to the capacitor is greater than its coercive voltage, then the capacitor may change polarization states depending on the polarity of the applied voltage. The polarization state is retained after power is removed, thus providing nonvolatility. A ferroelectric capacitor can be switched between polarization states in about one nanosecond, which is faster than the programming time of most other nonvolatile memories such as EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electrically Erasable Programmable Read Only Memories), or flash EEPROMs. However, like other nonvolatile memories, a ferroelectric memory cell can only endure a limited number of read/write cycles before losing the ability to store data.
FIG. 1 illustrates in schematic diagram form ferroelectric memory cell array 20 in accordance with the prior art. Ferroelectric memory cell array 20 includes a plurality of bit lines labeled "BL", a plurality of word lines labeled "WL", and a plurality of drive lines labeled "DL". Each memory cell includes an access transistor and a ferroelectric capacitor. For example, memory cell 22 includes access transistor 24 and ferroelectric capacitor 26. A gate of access transistor 24 is coupled to word line 23, a first current electrode is coupled to bit line 27, and a second current electrode is coupled to a first plate electrode of ferroelectric capacitor 26. A second plate electrode of ferroelectric capacitor 26 is coupled to drive line 25. The memory cells of array 20 are arranged in rows and columns. A row of memory cells comprises a word line and all of the memory cells that are coupled to the word line. A column of memory cells comprises a bit line and all of the memory cells that are coupled to the bit line. For example, word line 23 and memory cells 22, 28, 30, and 32 comprise a row, and bit line 27 and memory cells 22, 34, and 36 comprise a column. The word lines are used to access a memory cell, while the bit lines are used to read or write data to the accessed memory cell. Note that in FIG. 1, the drive lines are disposed substantially parallel to the word lines, and the memory cells of a row are coupled to the same drive line.
During a write cycle of a memory having array 20, a logic high signal is applied to a selected word line. The logic high signal causes the access transistors coupled to the selected word line to be conductive, thus coupling the ferroelectric capacitors to their respective bit lines. To write a logic one into a memory cell, the bit line coupled to a selected memory cell is pulled to a logic low voltage, usually ground potential, while the drive line coupled to the memory cell is pulled to a voltage approximately equal to the power supply voltage provided to array 20. This causes a voltage potential across the ferroelectric capacitor having a magnitude greater than the coercive voltage, thus semi-permanently polarizing the dielectric material of the capacitor in the direction of the electric field. To write a logic zero into a selected memory cell, the bit line that is coupled to the selected memory cell is pulled to a voltage equal to approximately the power supply voltage, while the voltage on the drive line is reduced to approximately ground potential. In this case, the voltage potential across the capacitor has a magnitude greater than the coercive voltage, but with the polarity in the opposite direction. During a write operation, the voltage on the drive line is pulled to a voltage equal to approximately the power supply voltage and then reduced to ground potential. Thus, the logic state to be written into a cell is controlled by the state of the bit line. This allows different logic states to be written into the cells along a selected row.
To read a selected memory cell, the voltage on the bit line coupled to the selected cell is reduced, or "precharged" to ground potential and then allowed to float. The drive line coupled to the selected memory cell provides a drive line signal having a logic high voltage equal to about the power supply voltage (for example, 5.0 volts). While the drive line signal is high, the word line coupled to the memory cell is pulled to a logic high voltage. This causes the access transistor of the cell to be conductive. The amount of current flow sensed on the bit line is used to determine the logic state stored in the ferroelectric capacitor of the memory cell. A sense amplifier (not shown) is used to drive the voltage on the bit line to ground if the sensed voltage corresponds to a logic one, or to the power supply voltage if the sensed voltage corresponds to a logic zero.
A read cycle of array 20 is a destructive read, since the logic state of all of the cells being read is changed to the same polarization state. Therefore, at the end of each read cycle, the data is restored by using the sensed logic state on the bit lines to rewrite the previously existing polarization state into each cell. This is accomplished by switching the drive line signal between a high voltage and ground potential while the word line is high and the bit line is still at the read logic state.
A problem with array 20 is that during a read cycle, all of the ferroelectric capacitors of a row are exposed to additional fatigue cycles which reduces their useful life. In addition, during both read and write cycles, a drive line voltage is provided to an entire row of memory cells, resulting in increased power consumption as the size of the array is increased.
FIG. 2 illustrates in schematic diagram form prior art ferroelectric memory cell array 40. Ferroelectric memory cell array 40 includes a plurality of bit lines labeled "BL", a plurality of word lines labeled "WL", and a plurality of drive lines labeled "DL". Like prior art memory array 20 of FIG. 1, each memory cell includes an access transistor and a ferroelectric capacitor. For example, memory cell 42, includes access transistor 44 and ferroelectric capacitor 46. A gate of access transistor 44 is coupled to word line 43, a first current electrode is coupled to bit line 47, and a second current electrode is coupled to a first plate electrode of ferroelectric capacitor 46. A second plate electrode of ferroelectric capacitor 46 is coupled to drive line 45. The memory cells of array 40 are also arranged in rows and columns. A row of memory cells comprises a word line and the memory cells that are coupled to the word line. A column of memory cells comprises a bit line and all of the memory cells that are coupled to the bit line. For example, word line 43 and memory cells 42, 48, 50, and 52 comprise a row, bit line 47 and memory cells 42, 54, and 56 comprise a column. In array 40, the drives lines are disposed substantially parallel to the bit lines, and the memory cells of a column are coupled to the same drive line. Memory array 40 is accessed for read and write cycles the same way as memory array 20. However, since the drive line is coupled to all of the cells of a column, during a read operation the unselected memory cells also receive a drive line voltage. If some of the cells of the column are storing a logic zero, the voltage potential on the drive line may change or, "disturb", the polarization of the ferroelectric capacitors coupled to the drive line. If such a polarization change of the ferroelectric capacitor of a cell is large enough, or if a series of read operations cause additional disturbing of the polarization state, a change in the logic state of the memory cells may result. In addition to the disturb problem of memory array 40, there may also be a space penalty for disposing the drive lines parallel to the bit lines.